Switching regulators can be used to convert an unregulated voltage to a desired, regulated DC voltage. FIG. 1 illustrates a schematic of a simple switching regulator 100 including an error amplifier 101 (e.g. a gm amplifier or another amplifier having a high output impedance), a modulator 102, a switching element 103, an LC filter 104, a load 105, and a compensation circuit 106.
In switching regulator 100, modulator 102 drives switching element 103 to provide one of VDD or VSS to LC filter 104. Specifically, a PMOS transistor 103A of switching element 103 is turned on (and an NMOS transistor 103B is turned off) to couple VDD to the input of inductor L of LC filter 104, thereby generating a ramped current through that inductor. At another point in time, NMOS transistor 103B is turned on (and PMOS transistor 103A is turned off) to couple VSS to the input of inductor L, thereby causing the current to ramp down until the start of a new switching cycle.
The amount of time that switching element 103 is “on” (i.e. PMOS transistor 103A being turned on) versus the total period is called the duty cycle. The duty cycle determines the output voltage Vout at a particular load current. Note that the capacitor C and the inductor L of LC filter 104 are sized to reduce voltage ripple of Vout. Load 105 is shown as a resistor R for purposes of illustration.
Error amplifier 101 receives voltage Vout on its negative input terminal and a reference voltage REF on its positive input terminal. Compensation circuit 106, which includes a resistor and a capacitor in this embodiment, is connected to the output terminal of error amplifier 101. In this configuration, error amplifier 101 can modify its output based on the difference between voltage Vout and reference voltage REF. The output of error amplifier 101 is provided to modulator 102, which can change the duty cycle of switching element 103 to minimize such difference.
There are numerous challenges in switching regulator design. The most basic challenge is obtaining a stable frequency response without undue restriction on external inductor and capacitor types/values (i.e. with respect to LC filter 104). This problem arises because LC filter 104 has two potentially low frequency poles (provided by inductor L and capacitor C) well below the unity gain bandwidth of switching regulator 100. Notably, if error amplifier 101 provides high gain, as can the case when using voltage mode pulse width modulation (PWM) for switching regulator 100, then error amplifier 101 introduces yet another low frequency pole.
To compensate for the three low frequency poles, a designer must include at least two zeros wherein compensation circuit 106 provides only one zero (via the resistor and capacitor therein). In one embodiment, the second zero can be designed into a more complex error amplifier 101. Alternatively, the designer can rely on the ESR (equivalent series resistance) of capacitor C in LC filter 104 to introduce the second zero (note that the capacitor C actually includes some parasitic resistance, which at some high frequency provides an additional zero). This option is simpler than designing a new error amplifier, but places restrictions on the type of capacitor that can be used by a customer in LC filter 104. If the customer fails to adhere to such restrictions, the loss and output ripple of switching regulator 100 may undesirably increase. Further, the wrong type of capacitor in LC filter 104 can even cause regulator instability.
Current mode PWM was developed to simplify switching regulator loop dynamics. FIG. 2 illustrates a switching regulator 200 using current mode PWM (note that elements having an identical or substantially identical function are labeled with the same reference numbers). In current mode PWM, switching regulator 200 uses a current loop 201 to control the inductor current and a voltage loop 202 to control the output voltage (described in reference to switching regulator 100 in FIG. 1).
In this embodiment, the inductor current is sensed with a small resistor Rsense and a current sense amplifier 203 having input terminals connected to both terminals of resistor Rsense. The output terminal of current sense amplifier 203 is connected to a negative input terminal of a PWM comparator 204 via current loop 201. The positive input terminal of PWM comparator 204 is coupled to the output terminal of error amplifier 101 via a summing block 208 (described in further detail below). The output terminal of PWM comparator 204 is connected to a reset terminal of a set/reset circuit 205. A set terminal of set/reset circuit 205 receives an oscillator signal 206. The output terminal of set/reset circuit 205 is buffered by a driver 207, which has an output terminal connected to resistor Rsense. Note that driver 207 can perform the functions associated with switching element 103 (FIG. 1), whereas PWM comparator 204, set/reset circuit 205, current sense amplifier 203, and resistor Rsense can perform the functions associated with modulator 102.
In this configuration, set/reset circuit 205 sets the PWM output periodically (using oscillator signal 206) and only resets the PWM output when the peak inductor current reaches a value set by voltage loop 202. Because the inductor current can be effectively controlled, the inductor current does not play a role in the loop dynamics. Therefore, from a small signal perspective, the inductor current can be replaced with a transconductance equal to 1/Rsense. As a result, good phase margin can be achieved with a single compensating zero and the ESR of capacitor C (in LC filter 104) is not restricted.
Unfortunately, current mode PWM suffers from an additional problem. Specifically, current loop 201 is unstable if the PWM duty cycle is greater than 50%. The duty cycle is determined by the regulator input voltage, output voltage Vout, and to a lesser extent the amount of power delivered to load 105. For duty cycles greater than 50%, the instability of current loop 201 can cause an undesirable sub-harmonic oscillation in the PWM and output voltage waveforms.
A technique called slope compensation was developed to mitigate this sub-harmonic oscillation. In switching regulator 200, summing block 208 can perform such slope compensation by introducing a periodic saw-tooth waveform to the output of error amplifier 101 (and thus to the input of PWM comparator 204). If the slope of the saw-tooth waveform is set properly, then inner loop 201 can be critically damped so that perturbations of the inductor current are corrected within a single cycle.
The correct slope for critical damping depends on the derivative of the inductor discharge current, which in turn depends on the output voltage Vout and the inductance L. That is, slope compensation works best if the slope of the saw-tooth waveform matches a value that depends on the output voltage Vout of inductor L. This matching requirement can place undesirable restrictions on both the output voltage Vout and the inductance L for a given switch regulator design. Moreover, to produce a saw-tooth waveform (and other necessary waveforms at appropriate points in the rest of the control circuit, not described herein), current mode PWM may require the design of complicated circuitry, e.g. summing block 208.
Note that if the slope compensation of summing block 208 is not set properly, then many cycles of oscillator 206 may be required for transients (i.e. current perturbations) to settle. Because of these additional cycles, voltage loop 202 must have a lower bandwidth than otherwise necessary.
Therefore, a need arises for a switching regulator that simplifies switching regulator loop dynamics without the need for slope compensation and without restrictions on output voltage and external components.